1. Field of the Invention
The present invention relates to a semiconductor device, and particularly a semiconductor device including a CMOS circuit.
2. Description of the Background Art
As a result of miniaturization of transistors, breakdown voltages of the transistors decrease, and therefore operation voltages must be necessarily lowered. In addition, portables must operate with a low voltage and a low power because portables are generally configured to operate on batteries.
In general, the operation speed lowers if the operation voltage is lowered. Therefore, it is necessary to lower threshold voltages of MOS transistors for achieving the low-voltage operation without impairing the operation speed. However, if the threshold voltage were excessively lowered, the transistor could not be cut off sufficiently, and an unignorable sub-threshold current would flow even during the off state of the transistor. This would impair low-voltage characteristics which are the most distinctive feature of conventional CMOS circuit.
FIG. 20 is a circuit diagram showing a structure of an inverter 500 in a conventional semiconductor device.
Referring to FIG. 20, inverter 500 includes a P-channel MOS transistor 501 which receives on its gate an input signal IN, and has a source coupled to a power supply potential Vdd, and an N-channel MOS transistor 502 which receives input signal IN on its gate, and has a source coupled to a ground potential Vss and a drain coupled to the drain of P-channel MOS transistor 501.
The potential on the drain of N-channel MOS transistor 502 provides an output signal OUT. The operation speed of the transistor is inversely proportional to (Vdd-Vt) where Vt represents a threshold voltage of N-channel MOS transistor 502. For suppressing reduction in speed, therefore, it is necessary to lower threshold voltage Vt in accordance with lowering of power supply potential Vdd.
However, excessively low threshold voltage Vt results in such a situation that an unignorable sub-threshold current IL flows through N-channel MOS transistor 502 even when a potential of 0 volts is applied as input signal IN.
FIG. 21 shows a relationship between a gate-source voltage VGS and a drain current IDS of the N-channel MOS transistor.
Particularly, FIG. 21 shows a change in drain current which occurs when gate-source voltage VGS changes at and around threshold voltage Vt, and the ordinate gives the drain current on a logarithmic scale.
On a graph or curve 504 in FIG. 21, it is assumed that the gate-source voltage is equal to threshold voltage Vt when a constant current IO flows through the transistor. Description is now be given on the case where an N-channel MOS transistor having a threshold voltage Vt2 lower than threshold voltage Vt is used for allowing use with a lower power supply voltage. A graph or curve 506 represents a relationship between the drain current and the gate-source voltage of the above N-channel MOS transistor. From comparison between the values which the drain current takes on graphs 504 and 506 when gate-source voltage VGS is 0 volts, drain current IDS on graph 506 is IL2 which is higher than IL on graph 504. Accordingly, in the structures which have higher integration densities and operate with lower power supply voltages and lower operation voltages, the sub-threshold current cannot be ignored, and increase in standby current results in a critical problem in battery-powered portables.
FIG. 22 is a circuit diagram showing an inverter 510, which can reduce a sub-threshold current by switching the source voltage, as is already proposed.
Referring to FIG. 22, inverter 510 includes an inverter 511 which has a power supply node coupled to power supply potential Vdd and a ground node connected to a node N100 for receiving input signal IN and issuing output signal OUT, and an N-channel MOS transistor 516 which receives on its gate a control signal SC, and has a drain connected to node N100 and a source connected to ground potential Vss.
Inverter 511 includes a P-channel MOS transistor 512 which receives input signal IN on its gate, and has a source connected to the power supply node and a drain connected to the output node, and an N-channel MOS transistor 514 which receives input signal IN on its gate, and has a source connected to node N100 and a drain connected to the output node.
FIGS. 23A and 23B show different types of transistors. FIG. 23A shows a symbol of a high-Vt transistor having a high threshold voltage Vt, and FIG. 23B shows a symbol of a low-Vt transistor having a low threshold voltage.
In the specification and drawings, the symbol of a transistor 518 shown in FIG. 23A represents a transistor of a high threshold voltage, and the symbol of a transistor 520 shown in FIG. 23B represents a transistor of a low threshold voltage.
Referring to FIG. 22 again, this circuit performs the normal operation in such a manner that control signal SC turns on N-channel MOS transistor 516, and a potential VN on node N100 is set to the ground potential so that inverter 511 performs a normal logical operation.
When the potential applied as input signal IN is at a L-level (low level), P-channel MOS transistor 512 is turned on, and N-channel MOS transistor 514 is turned off so that the output potential of output signal OUT attains a H-level (high level). In this case, a sub-threshold current flows through N-channel MOS transistor 514 in the off state, and the sub-threshold current causes a current flow from the power supply node supplied with power supply potential Vdd to the ground node supplied with ground potential Vss.
When input signal IN is at H-level, P-channel MOS transistor 512 is off, and N-channel MOS transistor 514 is on so that output signal OUT is at L-level. In this case, a sub-threshold current flows through P-channel MOS transistor 512 in the off state, and a sub-threshold current flows from the power supply node to the ground node. As described above, power consumption due to the sub-threshold current is inevitable in the normal operation.
However, the above circuit can reduce the power consumption due to the sub-threshold current while it can be determined in advance that the input logic is fixed and, for example, while the chip is on standby.
Assuming that the circuit is on standby when input signal IN is at L-level, P-channel MOS transistor 512 is on, and N-channel MOS transistor 514 is off. In this state, output signal OUT is at H-level.
When control signal SC is switched from H-level to L-level for switching the control from the operating state to the standby state, N-channel MOS transistor 516 is turned off. Since the threshold voltage of N-channel MOS transistor 516 is larger in absolute value than that of N-channel MOS transistor 514, the sub-threshold current caused by N-channel MOS transistor 516 is almost negligible compared with the sub-threshold current flowing through N-channel MOS transistor 514.
Accordingly, the current flowing from the power supply node to the ground node depends on the sub-threshold current of N-channel MOS transistor 516 so that the power consumption due to the sub-threshold current during standby can be reduced.
Even if N-channel MOS transistor 516 has a high threshold voltage, this does not affect the operation speed of inverter 511 when N-channel MOS transistor 516 is on. A high speed is not required in switching from the operating speed to the standby state, compared with the operation speed of inverter 511. Therefore, the high threshold voltage and low (but not excessively low) operation speed of N-channel MOS transistor 516 do not cause a problem.
As described above, when input signal IN is at L-level, control signal SC can be appropriately determined to set the circuit in the standby state while statically holding the output potential of output signal OUT. Conversely, when input signal IN is at H-level, P-channel MOS transistor having a high threshold voltage is arranged on the power supply node side of inverter 511, whereby a similar effect can be achieved.
FIG. 24 is a circuit diagram showing a structure of a circuit 530 which employs inverters connected in series and each having the structure shown in FIG. 22.
Referring to FIG. 24, circuit 530 includes an inverter 536 which receives and inverts input signal IN, and issues the same to a node N106, an inverter 538 which receives and inverts the potential on node N106, and issues the same to a node N108, an inverter 540 which receives and inverts the potential on node N108, and issues the same to a node N110, and an inverter 542 which receives and inverts the potential on node N110, and issues output signal OUT. This circuit also includes a P-channel MOS transistor 532 which receives a control signal ZSC on its gate, and has a source coupled to power supply potential Vdd and a drain connected to a node N102, and an N-channel MOS transistor 534 which receives control signal SC on its gate, and has a source coupled to ground potential Vss and a drain connected to a node N104.
Power supply nodes of inverters 536 and 540 are connected to power supply potential Vdd. Power supply nodes of inverters 538 and 542 are connected to node N102. Ground nodes of inverters 536 and 540 are connected to node N104. Ground nodes of inverters 538 and 542 are coupled to ground potential Vss.
P-channel MOS transistor 532 has a threshold voltage larger in absolute value than those of P-channel MOS transistors included in inverters 536-542. N-channel MOS transistor 534 has a threshold voltage larger in absolute value than those of N-channel MOS transistors included in inverters 536-542.
Structures of inverters 536-542 are similar to that of inverter 510 shown in FIG. 22, and therefore description will not be repeated.
An operation of circuit 530 is described below.
In the normal operation, control signal ZSC at L-level is applied to circuit 530, and potential VP on node N102 becomes equal to power supply potential Vdd. Control signal SC applied to circuit 530 is at H-level, and potential VN on node N104 is at the ground potential. In this state, input signal IN is appropriately switched between H- and L-levels for performing logical operations.
During standby, control signal ZSC is set to H-level so that node N102 is isolated from the power supply node. Control signal SC is set to L-level so that node N104 is isolated from the ground node. When input signal IN is at L-level, the control described above is performed so that the potentials on nodes N106 and N110 are held at power supply potential Vdd, and node N108 and output signal OUT are held at ground potential Vss.
As described above, the sub-threshold current can be reduced. For this purpose, however, it is necessary to provide the P-channel MOS transistor of a high threshold voltage on the power supply node side of the inverter or the N-channel MOS transistor of a high threshold voltage on the ground node side depending on the logical value which is held during standby of the circuit.
In the prior art, the circuit structure must be determined in accordance with the standby state of the circuit, as is done in circuit 530 shown in FIG. 24. However, this circuit structure suffers from such a problem that the logical value held on the node, to which the signal is transmitted during standby, cannot be held statically if the logical value is not uniquely determined. Assuming that circuit 530 is on standby when input signal IN is at H-level, node N106 is in the high impedance state, and the potential on node N106 will become unstable with time.
When designing the circuit, consideration must be given to the standby state, and designing steps are disadvantageously required for arranging a transistor of a high threshold voltage on either the power supply node side or the ground node side for reducing the sub-threshold current.